Sub-10nm tunnel field-effect transistor with graded Si/Ge heterojunction

This study presents a new sub-10-nm tunnel field-effect transistor (TFET) with bandgap engineering using a graded Si/Ge heterojunction. Both the height and width of the tunneling barrier are highly controlled by applying gate voltages to ensure a near ideal sub-5-mV/dec switching of scaled sub-10-nm...

Mô tả đầy đủ

Đã lưu trong:

Chi tiết về thư mục
Những tác giả chính:	Chun-Hsing Shih, Nguyễn, Đăng Chiến
Định dạng:	Journal article
Ngôn ngữ:	English
Được phát hành:	IEEE Publishing 2024
Những chủ đề:	Bandgap engineering Graded Si/Ge heterojunction Short-channel effect Tunnel field-effect transistor
Truy cập trực tuyến:	https://scholar.dlu.edu.vn/handle/123456789/3297
Các nhãn:	Thêm thẻ Không có thẻ, Là người đầu tiên thẻ bản ghi này!

Thư viện lưu trữ:	Thư viện Trường Đại học Đà Lạt

id	oai:scholar.dlu.edu.vn:123456789-3297
record_format	dspace
institution	Thư viện Trường Đại học Đà Lạt
collection	Thư viện số
language	English
topic	Bandgap engineering Graded Si/Ge heterojunction Short-channel effect Tunnel field-effect transistor
spellingShingle	Bandgap engineering Graded Si/Ge heterojunction Short-channel effect Tunnel field-effect transistor Chun-Hsing Shih Nguyễn, Đăng Chiến Sub-10nm tunnel field-effect transistor with graded Si/Ge heterojunction
description	This study presents a new sub-10-nm tunnel field-effect transistor (TFET) with bandgap engineering using a graded Si/Ge heterojunction. Both the height and width of the tunneling barrier are highly controlled by applying gate voltages to ensure a near ideal sub-5-mV/dec switching of scaled sub-10-nm TFETs at 300 K. This study performed a 2-D simulation to elucidate p-body graded Si/Ge heterojunction TFET devices from 50 to 5 nm. The on-state tunneling barrier around the source was narrowed and lowered to demonstrate a high on-current; simultaneously, the off-state tunneling barrier was raised and extended into the drain to control the short-channel effect and ambipolar leakage current. The shorter the length is, the more abrupt is the switching. The breakthrough in subthreshold swing and short-channel effect make the graded Si/Ge TFET highly promising as an ideal green transistor into sub-10-nm regimes.
format	Journal article
author	Chun-Hsing Shih Nguyễn, Đăng Chiến
author_facet	Chun-Hsing Shih Nguyễn, Đăng Chiến
author_sort	Chun-Hsing Shih
title	Sub-10nm tunnel field-effect transistor with graded Si/Ge heterojunction
title_short	Sub-10nm tunnel field-effect transistor with graded Si/Ge heterojunction
title_full	Sub-10nm tunnel field-effect transistor with graded Si/Ge heterojunction
title_fullStr	Sub-10nm tunnel field-effect transistor with graded Si/Ge heterojunction
title_full_unstemmed	Sub-10nm tunnel field-effect transistor with graded Si/Ge heterojunction
title_sort	sub-10nm tunnel field-effect transistor with graded si/ge heterojunction
publisher	IEEE Publishing
publishDate	2024
url	https://scholar.dlu.edu.vn/handle/123456789/3297
_version_	1798256981691072512
spelling	oai:scholar.dlu.edu.vn:123456789-32972024-03-01T07:47:31Z Sub-10nm tunnel field-effect transistor with graded Si/Ge heterojunction Chun-Hsing Shih Nguyễn, Đăng Chiến Bandgap engineering Graded Si/Ge heterojunction Short-channel effect Tunnel field-effect transistor This study presents a new sub-10-nm tunnel field-effect transistor (TFET) with bandgap engineering using a graded Si/Ge heterojunction. Both the height and width of the tunneling barrier are highly controlled by applying gate voltages to ensure a near ideal sub-5-mV/dec switching of scaled sub-10-nm TFETs at 300 K. This study performed a 2-D simulation to elucidate p-body graded Si/Ge heterojunction TFET devices from 50 to 5 nm. The on-state tunneling barrier around the source was narrowed and lowered to demonstrate a high on-current; simultaneously, the off-state tunneling barrier was raised and extended into the drain to control the short-channel effect and ambipolar leakage current. The shorter the length is, the more abrupt is the switching. The breakthrough in subthreshold swing and short-channel effect make the graded Si/Ge TFET highly promising as an ideal green transistor into sub-10-nm regimes. 32 11 1498-1500 2024-03-01T07:47:25Z 2024-03-01T07:47:25Z 2011 Journal article Bài báo đăng trên tạp chí thuộc ISI, bao gồm book chapter https://scholar.dlu.edu.vn/handle/123456789/3297 10.1109/LED.2011.2164512 en IEEE Electron Device Letters 0741-3106 P.-F. Wang, K. Hilsenbeck, Th. Nirschl, M. Oswald, Ch. Stepper, M. Weis, D. Schmitt-Landsiedel, and W. Hansch, “Complementary tunneling transistor for low power application”, Solid-State Electron., vol. 48, no. 12, pp. 2281-2286, Dec. 2004. [2] K. K. Bhuwalka, J. Schulze, and I. Eisele, “Performance enhancement of vertical tunnel field-effect transistor with SiGe in the layer”, Jpn. J. Appl. Phys., vol. 43, no. 7A, pp. 4073-4078, Jul. 2004. [3] W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec”, IEEE Electron Device Lett., vol. 28, no. 8, pp. 743-745, Aug. 2007. [4] E.-H. Toh, G. H. Wang, L. Chan, D. Sylvester, C.-H. Heng, G. S. Samudra, and Y.-C. Yeo, “Device design and scalability of a double-gate tunneling field-effect transistor with silicon–germanium source”, Jpn. J. Appl. Phys., vol. 47, no. 4, pp. 2593-2597, Apr. 2008. [5] K. Bhuwalka, M. Born, M. Schindler, M. Schmidt, T. Sulima and I. Eisele, “P-Channel tunnel field-effect transistors down to sub-50 nm channel lengths”, Jpn. J. Appl. Phys., vol. 45, no. 4B, pp. 3106-3109, Apr. 2006. [6] E.-H. Toh, G. H. Wang, G. Samudra, and Y.-C. Yeo, “Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications”, J. Appl. Phys., vol. 103, no. 10, p. 104504, May 2008. [7] W. Y. Choi and W. Lee, “Hetero-gate-dielectric tunneling field-Effect transistors”, IEEE Trans. Electron Devices, vol. 57, no. 9, pp. 2317-2319, Sep. 2010. [8] A. S. Verhulst, W. G. Vandenberghe, K. Maex, and G. Groeseneken, “Tunnel field-effect transistor without gate-drain overlap”, Appl. Phys. Lett., vol. 91, no. 5, p. 053102, Jul. 2007. [9] K. Boucart and A. M. Ionescu, “Length scaling of the double gate tunnel FET with a high-k gate dielectric”, Solid State Electron., vol. 51, no. 11/12, pp. 1500-1507, Nov./Dec. 2007. [10] T. Krishnamohan, K. Donghyun, S. Raghunathan, and K. Saraswat, “Double-gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and <60mV/dec subthreshold slope”, in IEEE International Electron Devices Meeting (IEDM), 2008, pp. 1-3. [11] Y. Khatami and K. Banerjee, “Steep subthreshold slope n- and p-type tunnel-FET devices for low-power and energy-efficient digital circuits”, IEEE Trans. Electron Devices, vol. 56, no. 11, pp. 2752-2761, Nov. 2009. [12] S. H. Kim, H. Kam, C. Hu, and T.-J. K. Liu, “Germanium-source tunnel field effect transistors with record high ION/IOFF”, in VLSI Symp. Tech. Dig., 2009, pp. 178–179. [13] H. G. Virani, R. B. Rao, and A. Kottantharayil, “Investigation of Novel Si-SiGe Heterostructures and Gate Induced Source Tunneling for Improvement of p-Channel Tunnel Field-Effect Transistors”, Jpn. J. Appl. Phys., vol. 49, No. 4, pp. 04DC12-04DC12-5, Apr. 2010. [14] M. G. Bardon, H. P. Neves, R. Puers, and C. V. Hoof, “Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions”, IEEE Trans. Electron Devices, vol. 57, pp. 827-834, Apr. 2010. [15] E.-H. Toh, G. H. Wang, G. Samudra, and Y.-C. Yeoa, “Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization”, Appl. Phys. Lett., vol. 90, no. 26, p. 263507, Jun. 2007. [16] Synopsys MEDICI User’s Manual, Synopsys Inc., Mountain View, CA, 2010. IEEE Publishing USA

Sub-10nm tunnel field-effect transistor with graded Si/Ge heterojunction

Những quyển sách tương tự