Schottky barrier silicon nanowire SONOS memory with ultralow programming and erasing voltages

A new Schottky barrier (SB) nonvolatile nanowire memory is reported experimentally with efficient low-voltage programming and erasing. By applying an SB source/drain to enhance the electrical field in the silicon gate-all-around nanowire, the nonvolatile silicon-oxide-nitride-oxide-silicon (SONOS) m...

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Những tác giả chính:	Chun-Hsing Shih, Wei Chang, Yan-Xiang Luo, Ji-Ting Liang, Ming-Kun Huang, Nguyễn, Đăng Chiến, Ruei-Kai Shia, Jr-Jie Tsai, Wen-Fa Wu, Chenhsin Lien
Định dạng:	Journal article
Ngôn ngữ:	English
Được phát hành:	IEEE Publishing 2024
Những chủ đề:	Gate-all-around nanowire Schottky barrier (SB) Silicon–oxide-nitride-oxide-silicon (SONOS) memory
Truy cập trực tuyến:	https://scholar.dlu.edu.vn/handle/123456789/3298
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id	oai:scholar.dlu.edu.vn:123456789-3298
record_format	dspace
institution	Thư viện Trường Đại học Đà Lạt
collection	Thư viện số
language	English
topic	Gate-all-around nanowire Schottky barrier (SB) Silicon–oxide-nitride-oxide-silicon (SONOS) memory
spellingShingle	Gate-all-around nanowire Schottky barrier (SB) Silicon–oxide-nitride-oxide-silicon (SONOS) memory Chun-Hsing Shih Wei Chang Yan-Xiang Luo Ji-Ting Liang Ming-Kun Huang Nguyễn, Đăng Chiến Ruei-Kai Shia Jr-Jie Tsai Wen-Fa Wu Chenhsin Lien Schottky barrier silicon nanowire SONOS memory with ultralow programming and erasing voltages
description	A new Schottky barrier (SB) nonvolatile nanowire memory is reported experimentally with efficient low-voltage programming and erasing. By applying an SB source/drain to enhance the electrical field in the silicon gate-all-around nanowire, the nonvolatile silicon-oxide-nitride-oxide-silicon (SONOS) memory can operate at gate voltages of 5 to 7 V for programming and -7 to -9 V for erasing through Fowler-Nordheim tunneling. The larger the gate voltage is, the faster the programming/erasing speed and the wider the threshold-voltage shift are attained. Importantly, the SB nanowire SONOS cells exhibit superior 100-K cycling endurance and high-temperature retention without any damages from metallic silicidation process or field-enhanced tunneling.
format	Journal article
author	Chun-Hsing Shih Wei Chang Yan-Xiang Luo Ji-Ting Liang Ming-Kun Huang Nguyễn, Đăng Chiến Ruei-Kai Shia Jr-Jie Tsai Wen-Fa Wu Chenhsin Lien
author_facet	Chun-Hsing Shih Wei Chang Yan-Xiang Luo Ji-Ting Liang Ming-Kun Huang Nguyễn, Đăng Chiến Ruei-Kai Shia Jr-Jie Tsai Wen-Fa Wu Chenhsin Lien
author_sort	Chun-Hsing Shih
title	Schottky barrier silicon nanowire SONOS memory with ultralow programming and erasing voltages
title_short	Schottky barrier silicon nanowire SONOS memory with ultralow programming and erasing voltages
title_full	Schottky barrier silicon nanowire SONOS memory with ultralow programming and erasing voltages
title_fullStr	Schottky barrier silicon nanowire SONOS memory with ultralow programming and erasing voltages
title_full_unstemmed	Schottky barrier silicon nanowire SONOS memory with ultralow programming and erasing voltages
title_sort	schottky barrier silicon nanowire sonos memory with ultralow programming and erasing voltages
publisher	IEEE Publishing
publishDate	2024
url	https://scholar.dlu.edu.vn/handle/123456789/3298
_version_	1798256982047588352
spelling	oai:scholar.dlu.edu.vn:123456789-32982024-03-01T07:55:16Z Schottky barrier silicon nanowire SONOS memory with ultralow programming and erasing voltages Chun-Hsing Shih Wei Chang Yan-Xiang Luo Ji-Ting Liang Ming-Kun Huang Nguyễn, Đăng Chiến Ruei-Kai Shia Jr-Jie Tsai Wen-Fa Wu Chenhsin Lien Gate-all-around nanowire Schottky barrier (SB) Silicon–oxide-nitride-oxide-silicon (SONOS) memory A new Schottky barrier (SB) nonvolatile nanowire memory is reported experimentally with efficient low-voltage programming and erasing. By applying an SB source/drain to enhance the electrical field in the silicon gate-all-around nanowire, the nonvolatile silicon-oxide-nitride-oxide-silicon (SONOS) memory can operate at gate voltages of 5 to 7 V for programming and -7 to -9 V for erasing through Fowler-Nordheim tunneling. The larger the gate voltage is, the faster the programming/erasing speed and the wider the threshold-voltage shift are attained. Importantly, the SB nanowire SONOS cells exhibit superior 100-K cycling endurance and high-temperature retention without any damages from metallic silicidation process or field-enhanced tunneling. 32 11 1477-1479 2024-03-01T07:55:10Z 2024-03-01T07:55:10Z 2011 Journal article Bài báo đăng trên tạp chí thuộc ISI, bao gồm book chapter https://scholar.dlu.edu.vn/handle/123456789/3298 10.1109/LED.2011.2164510 en IEEE Electron Device Letters 0741-3106 [1] S. D. Suk, K. H. Yeo, K. H. Cho, M. Li, Y. Y. Yeoh, K.-H. Hong, S.-H. Kim, Y.-H. Koh, S. Jung, W. J. Jang, D.-W. Kim, D. Park, and B.-I. Ryu, “Gate-all-around twin silicon nanowire SONOS memory,” in VLSI Symp. Tech. Dig., 2007, pp. 142–143. [2] J. Fu, N. Singh, K. D. Buddharaju, S. H. G. Teo, C. Shen, Y. Jiang, C. X. Zhu, M. B. Yu, G. Q. Lo, N. Balasubramanian, D. L. Kwong, E. Gnani, and G. Baccarani, “Si-nanowire based gate-all-around nonvolatile SONOS memory cell,”IEEE Electron Device Lett., vol. 29, no. 5, pp. 518–521, May 2008. [3] K.H.Yeo,K.H.Cho,M.Li,S.D.Suk,Y.-Y.Yeoh,M.-S.Kim, H. Bae, J.-M. Lee, S.-K. Sung, J. Seo, B. Park, D.-W. Kim, D. Park, and W.-S. Lee, “Gate-all-around single silicon nanowire MOSFET with 7 nm width for SONOSNANDFlash memory,” inVLSI Symp. Tech. Dig., 2008, pp. 138–139. [4] J. Fu, Y. Jiang, N. Singh, C. X. Zhu, G. Q. Lo, and D. L. Kwong, “Polycrystalline Si nanowire SONOS nonvolatile memory cell fabricated on a gate-all-around (GAA) channel architecture,”IEEE Electron Device Lett., vol. 30, no. 3, pp. 246–249, Mar. 2009. [5] D.-I. Moon, S.-J. Choi, C.-J. Kim, J.-Y. Kim, J.-S. Lee, J.-S. Oh, G.-S. Lee, Y.-C. Park, D.-W. Hong, D.-W. Lee, Y.-S. Kim, J.-W. Kim, J.-W. Han, and Y.-K. Choi, “Ultimately scaled 20 nm unified-RAM,” in IEDM Tech. Dig., 2010, pp. 284–287. [6] T.-C. Lia, S.-K. Chen, M. H. Yu, C.-Y. Wu, T.-K. Kang, F.-T. Chien, Y.-T. Liu, C.-M. Lin, and H.-C. Cheng, “A novel LTPS-TFT-based chargetrapping memory device with field-enhanced nanowire structure,” in IEDM Tech. Dig., 2009, pp. 207–210. [7] P.-C. Huang, L.-A. Chen, and J.-T. Sheu, “Electric-field enhancement of a gate-all-around nanowire thin-film transistor memory,”IEEE Electron Device Lett., vol. 31, no. 3, pp. 216–218, Mar. 2010. [8] M. Chen, H. Y. Yu, N. Singh, Y. Sun, N. S. Shen, X. Yuan, G.-Q. Lo, and D.-L. Kwong, “Vertical-Si-nanowire SONOS memory for ultrahighdensity application,”IEEE Electron Device Lett., vol. 30, no. 8, pp. 879–881, Aug. 2009. [9] C.-H. Shih and J.-T. Liang, “Nonvolatile Schottky barrier multibit cell with source-side injected programming and reverse drain-side hole erasing,” IEEE Trans. Electron Devices, vol. 57, no. 8, pp. 1774–1780, Aug. 2010. [10] K. Uchida, K. Matsuzawa, J. Koga, S. Takagi, and A. Toriumi, “Enhancement of hot-electron generation rate in Schottky source metal–oxide–semiconductor field-effect transistors,”Appl. Phys. Lett., vol. 76, no. 26, pp. 3992–3994, Jun. 2000. [11] C.-H. Shih, S.-P. Yeh, J.-T. Liang, and Y.-X. Luo, “Source-side injection Schottky barrier Flash memory cells,”Semicond. Sci. Technol., vol. 24, no. 2, p. 025 013, Feb. 2009. [12] S.-J. Choi, J.-W. Han, S. Kim, D.-H. Kim, M.-G. Jang, J.-H. Yang, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.-K. Choi, “High speed Flash memory and 1T-DRAM on dopant segregated Schottky barrier (DSSB) FinFET SONOS device for multi-functional SoC applications,” in IEDM Tech. Dig., 2008, pp. 223–226. [13] S.-J. Choi, J.-W. Han, S. Kim, M.-G. Jang, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.-K. Choi, “Enhancement of program speed in dopant-segregated Schottky-barrier (DSSB) FinFET SONOS forNAND-type Flash memory,”IEEE Electron Device Lett., vol. 30, no. 1, pp. 78–81, Jan. 2009. [14] H. Iwai, T. Ohguro, and S.-I. Ohmi, “NiSi salicide technology for scaled CMOS,”Microelectron. Eng., vol. 60, no. 1/2, pp. 157–169, Jan. 2002. [15] C.-F. Huang and B.-Y. Tsui, “Short-channel metal-gate TFTs with modified Schottky-barrier source/drain,” IEEE Electron Device Lett., vol. 27, no. 1, pp. 43–45, Jan. 2006. IEEE Publishing USA

Schottky barrier silicon nanowire SONOS memory with ultralow programming and erasing voltages

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