A source-side injection lucky electron model for Schottky barrier metal-oxide-semiconductor devices
This letter explores source-side injection in Schottky barrier metal-oxide-semiconductor (MOS) devices. Unlike drain-side injection in conventional MOS devices, a source-side lucky electron model predicts the specific source-side injection in Schottky barrier MOS devices. The source-side electric fi...
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Lucky electron model Metal–oxide– semiconductor (MOS) Schottky barrier Source-side injection |
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Lucky electron model Metal–oxide– semiconductor (MOS) Schottky barrier Source-side injection Chun-Hsing Shih Ji-Ting Liang Jhong-Sheng Wang Nguyễn, Đăng Chiến A source-side injection lucky electron model for Schottky barrier metal-oxide-semiconductor devices |
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This letter explores source-side injection in Schottky barrier metal-oxide-semiconductor (MOS) devices. Unlike drain-side injection in conventional MOS devices, a source-side lucky electron model predicts the specific source-side injection in Schottky barrier MOS devices. The source-side electric field is derived from the solutions of 2-D Poisson's equations. The conformal-mapping method is used to estimate the gate electrode contribution to determine the source-side injected probability. 2-D device simulations confirm the agreements between the analytical models and the numerical results. This study provides a physical understanding of enhanced source-side injection in new Schottky barrier nonvolatile memory. |
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Journal article |
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Chun-Hsing Shih Ji-Ting Liang Jhong-Sheng Wang Nguyễn, Đăng Chiến |
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Chun-Hsing Shih Ji-Ting Liang Jhong-Sheng Wang Nguyễn, Đăng Chiến |
author_sort |
Chun-Hsing Shih |
title |
A source-side injection lucky electron model for Schottky barrier metal-oxide-semiconductor devices |
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A source-side injection lucky electron model for Schottky barrier metal-oxide-semiconductor devices |
title_full |
A source-side injection lucky electron model for Schottky barrier metal-oxide-semiconductor devices |
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A source-side injection lucky electron model for Schottky barrier metal-oxide-semiconductor devices |
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A source-side injection lucky electron model for Schottky barrier metal-oxide-semiconductor devices |
title_sort |
source-side injection lucky electron model for schottky barrier metal-oxide-semiconductor devices |
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IEEE Publishing |
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2024 |
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https://scholar.dlu.edu.vn/handle/123456789/3299 |
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oai:scholar.dlu.edu.vn:123456789-32992024-03-01T08:02:39Z A source-side injection lucky electron model for Schottky barrier metal-oxide-semiconductor devices Chun-Hsing Shih Ji-Ting Liang Jhong-Sheng Wang Nguyễn, Đăng Chiến Lucky electron model Metal–oxide– semiconductor (MOS) Schottky barrier Source-side injection This letter explores source-side injection in Schottky barrier metal-oxide-semiconductor (MOS) devices. Unlike drain-side injection in conventional MOS devices, a source-side lucky electron model predicts the specific source-side injection in Schottky barrier MOS devices. The source-side electric field is derived from the solutions of 2-D Poisson's equations. The conformal-mapping method is used to estimate the gate electrode contribution to determine the source-side injected probability. 2-D device simulations confirm the agreements between the analytical models and the numerical results. This study provides a physical understanding of enhanced source-side injection in new Schottky barrier nonvolatile memory. 32 10 1331 - 1333 2024-03-01T08:02:33Z 2024-03-01T08:02:33Z 2011 Journal article Bài báo đăng trên tạp chí thuộc ISI, bao gồm book chapter https://scholar.dlu.edu.vn/handle/123456789/3299 10.1109/LED.2011.2162577 en IEEE Electron Device Letters 0741-3106 [1] S. D. Suk, K. H. Yeo, K. H. Cho, M. Li, Y. Y. Yeoh, K.-H. Hong, S.-H. Kim, Y.-H. Koh, S. Jung, W. J. Jang, D. W. Kim, D. Park, and B.-I. Ryu, “Gate-all-around twin silicon nanowire SONOS memory,” in VLSI Symp. Tech. Dig., 2007, pp. 142–143. [2] J. Fu, N. Singh, K. D. Buddharaju, S. H. G. Teo, C. Shen, Y. Jiang, C. X. Zhu, M. B. Yu, G. Q. Lo, N. Balasubramanian, D. L. Kwong, E. Gnani, and G. Baccarani, “Si-nanowire based gate-all-around nonvolatile SONOS memory cell,”IEEE Electron Device Lett., vol. 29, no. 5, pp. 518–521, May 2008. [3] K.H.Yeo,K.H.Cho,M.Li,S.D.Suk,Y.-Y.Yeoh,M.-S.Kim, H. Bae, J.-M. Lee, S.-K. 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