Different scalabilities of N- and P-Type tunnel field-effect transistors with Si/SiGe heterojunctions
The dimensional scaling of tunnel field-effect transistors (TFETs) is an indispensable issue to make them competitive with traditional metal-oxide-semiconductor field-effect transistors (MOSFETs). This paper elucidates the scalabilities of very potential TFETs utilizing Si/SiGe heterojunctions opera...
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Short-channel effect device scaling Si/SiGe heterojunction tunnel field-effect transistor (TFET) |
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Short-channel effect device scaling Si/SiGe heterojunction tunnel field-effect transistor (TFET) Nguyễn, Đăng Chiến Nguyen Thi Thu Chun-Hsing Shih Luu The Vinh Different scalabilities of N- and P-Type tunnel field-effect transistors with Si/SiGe heterojunctions |
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The dimensional scaling of tunnel field-effect transistors (TFETs) is an indispensable issue to make them competitive with traditional metal-oxide-semiconductor field-effect transistors (MOSFETs). This paper elucidates the scalabilities of very potential TFETs utilizing Si/SiGe heterojunctions operated in n- and p-type operation modes. Although using the Si/SiGe heterostructures helps to improve the on-currents of both n- and p-type TFETs, its assistance in scaling the device dimension is essentially different between the n- and p-type modes. The asymmetric band-offset of Si/SiGe heterojunctions associated with the asymmetric properties of tunneling in n- and p-type TFETs are responsible for the scalability difference. With a high scalability down to sub-10 nm, the graded Si/SiGe heterojunction p-type TFET exhibits a feasible candidate for low-power and highly-scaled integrated circuits. |
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Conference paper |
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Nguyễn, Đăng Chiến Nguyen Thi Thu Chun-Hsing Shih Luu The Vinh |
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Nguyễn, Đăng Chiến Nguyen Thi Thu Chun-Hsing Shih Luu The Vinh |
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Nguyễn, Đăng Chiến |
| title |
Different scalabilities of N- and P-Type tunnel field-effect transistors with Si/SiGe heterojunctions |
| title_short |
Different scalabilities of N- and P-Type tunnel field-effect transistors with Si/SiGe heterojunctions |
| title_full |
Different scalabilities of N- and P-Type tunnel field-effect transistors with Si/SiGe heterojunctions |
| title_fullStr |
Different scalabilities of N- and P-Type tunnel field-effect transistors with Si/SiGe heterojunctions |
| title_full_unstemmed |
Different scalabilities of N- and P-Type tunnel field-effect transistors with Si/SiGe heterojunctions |
| title_sort |
different scalabilities of n- and p-type tunnel field-effect transistors with si/sige heterojunctions |
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IEEE Publishing |
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2024 |
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https://scholar.dlu.edu.vn/handle/123456789/3312 |
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1798256988256206848 |
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oai:scholar.dlu.edu.vn:123456789-33122024-03-02T11:32:18Z Different scalabilities of N- and P-Type tunnel field-effect transistors with Si/SiGe heterojunctions Nguyễn, Đăng Chiến Nguyen Thi Thu Chun-Hsing Shih Luu The Vinh Short-channel effect device scaling Si/SiGe heterojunction tunnel field-effect transistor (TFET) The dimensional scaling of tunnel field-effect transistors (TFETs) is an indispensable issue to make them competitive with traditional metal-oxide-semiconductor field-effect transistors (MOSFETs). This paper elucidates the scalabilities of very potential TFETs utilizing Si/SiGe heterojunctions operated in n- and p-type operation modes. Although using the Si/SiGe heterostructures helps to improve the on-currents of both n- and p-type TFETs, its assistance in scaling the device dimension is essentially different between the n- and p-type modes. The asymmetric band-offset of Si/SiGe heterojunctions associated with the asymmetric properties of tunneling in n- and p-type TFETs are responsible for the scalability difference. With a high scalability down to sub-10 nm, the graded Si/SiGe heterojunction p-type TFET exhibits a feasible candidate for low-power and highly-scaled integrated circuits. 1-4 2024-03-02T11:32:09Z 2024-03-02T11:32:09Z 2016 Conference paper Bài báo đăng trên KYHT quốc tế (có ISBN) 978-1-5090-0321-1 https://scholar.dlu.edu.vn/handle/123456789/3312 10.1109/ICICDT.2016.7542055 en Nghiên cứu cơ chế, đặc tính và phương pháp giảm hiệu ứng kênh ngắn trong các transistor trường xuyên hầm sử dụng vật liệu vùng cấm nhỏ International Conference on IC Design and Technology (ICICDT) B2016-03 [1] S.-Y. Wu et al., “An enhanced 16nm CMOS technology featuring 2nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications,” in IEDM Tech. Dig., 2014, pp. 3.1.1-4. [2] B. J. Lin, “Lithography till the end of Moore’s law,” in Proc. of the ACM Int. Symp. on Physical Design (ISPD), 2012, pp. 1-2. [3] W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec,” IEEE Electron Device Lett., vol. 28, no. 8, pp. 743-745, Aug. 2007. [4] H. Fuketa, K. Yoshioka, K. Fukuda, T. Mori, H. Ota, M. Takamiya, and T. Sakurai, “Design guidelines to achieve minimum energy operation for ultra low voltage tunneling FET logic circuits,” Jpn. J. Appl. Phys., vol. 54, no. 4S, p. 04DC04, Apr. 2015. [5] L. Knoll, M. Schmidt, Q. T. Zhao, S. Trellenkamp, A. Schafer, K. K. Bourdelle, and S. Mantl, “Si tunneling transistors with high on-currents and slopes of 50 mV/dec using segregation doped NiSi2 tunnel junctions,” Solid-State Electron., vol. 84, pp. 211-215, Jun. 2013. [6] T. Krishnamohan, K. Donghyun, S. Raghunathan, and K. Saraswat, “Double-gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and <60mV/dec subthreshold slope,” in IEDM Tech. Dig., 2008, pp. 1-3. [7] N. Surana, B. Ghosh, B. M. M. Tripathy, and A. K. Salimath, “A silicon germanium graded junctionless transistor with low off current,” International Journal of Nanoscience, vol. 12, no. 6, p. 1350043, Feb. 2013. [8] C.-H. Shih and N. D. Chien, “Physical operation and device design of short-channel tunnel field-effect transistors with graded silicon-germanium heterojunctions,” J. Appl. Phys., vol. 113, no. 13, p. 134507, Apr. 2013. [9] Synopsys MEDICI User’s Manual, Synopsys Inc., Mountain View, CA, 2010. [10] E. O. Kane, “Theory of tunneling,” J. Appl. Phys., vol. 31, no. 1, pp. 83-91, 1961. [11] N. D. Chien, L. T. Vinh, N. V. Kien, R.-K. Shia, T.-S. Kang, and C.-H. Shih, “Proper determination of tunnel model parameters for indirect band-to-band tunneling in compressively strained Si1-xGex TFETs,” in Proc. of IEEE Int. Symp. on Next-Generation Electronics (ISNE), 2013, pp. 67-70. [12] N. D. Chien, C.-H. Shih, L. T. Vinh, and N. V. Kien, “Quantum confinement effect in strained-Si1-xGex double-gate tunnel field-Effect transistors,” in Proc. of IEEE Int. Conf. on IC Design and Technology (ICICDT), 2013, pp. 73-76. [13] K. Kim and Y. H. Lee, “Temperature‐dependent critical layer thickness for strained‐layer heterostructures,” Appl. Phys. Lett., vol. 67, pp. 2212-2214, Aug. 1995. [14] N. D. Chien, C.-H. Shih, and Luu The Vinh, “Drive current enhancement in tunnel field-effect transistors by graded heterojunction approach,” J. Appl. Phys., vol. 114, no. 9, p. 094507, Sep. 2013 [Erratum, vol. 114, no. 18, p. 189901, Nov. 2013]. [15] E.-H. Toh, G. H. Wang, G. Samudra, and Y.-C. Yeo, “Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications,” J. Appl. Phys., vol. 103, no. 10, p. 104504, May 2008. [16] E.-H. Toh, G.-H. Wang, and Y.-C. Yeo, “Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction,” Appl. Phys. Lett., vol. 91, no. 24, p. 243505, Dec. 2007. IEEE Publishing USA |